In prior art computer systems employing micro-machines which are clocked asynchronously from the system with which they are interfaced (i.e. wherein the clock of the micro-machine is out of phase or has a different period than the clock running the system with which the micro-machine is interfaced), latency (the time lag between the time of issuance of an incoming instruction to the micro-machine and the time of instruction completion) is a critical and troublesome problem. For purposes of the Specification herein, the term "micro-machine" or asynchronous micro-machine is defined as a computational computer system which includes a command or instruction register which is typically updated at every clock cycle with commands that are read from a microstore memory and which are used to execute an incoming instruction. These commands typically are comprised of control signals as well as data.
In order to overcome the problem of latency which occurs in micro-machines that run asynchronously from the CPU from which the micro-machine receives its instructions, prior art systems employ various synchronization interfacing circuitry between the master CPU and the asynchronous micro-machine. Such prior art synchronization interfaces generally hold the incoming instruction issued by the CPU, synchronize the instruction to the clock of the micro-machine and, at the completion of the synchronization process, set a flag bit which informs the micro-machine that an instruction is waiting. The micro-machine then, in turn, transfers control (changes addresses) to the routine that corresponds to the incoming, now synchronized, instruction. The two primary examples of such prior art synchronization interfaces are "FIFO" and shared memory systems.
However, with all such prior art synchronization systems, synchronization of the incoming instruction and transfer of control by the micro-machine to the routine of the instruction occurs substantially consecutively, such that the length of time it takes to synchronize the incoming instruction and the length of time it takes the micro-machine to transfer control to the routine that corresponds to the instruction are cumulative. Further, no actions are taken for that instruction until transfer of control by the micro-machine takes place. Therefore, latency is merely reduced and is not minimized. Accordingly, in all prior art systems employing asynchronous micro-coded machines, latency remains a critical and unsolved problem.